Attempts continue to shrink the dimensions for fabricating MOS transistors. Devices having sub-micrometer dimensions permit closer placement of devices, thereby increasing the density of devices on a chip and also increasing device operating speed.
There are many types of lightly-doped drain (LDD) transistors presently in use, which are reviewed by A. F. Tasch et at, IEEE Electron Device Letters, Vol. 11, No. 11, pp. 517-519 (1990). In order to reduce the dimensions even further, based on device simulations, it appears that the scaled device must have shallow N.sup.- LDD junctions to overcome charge sharing and doping compensation effects. This permits devices with acceptable short channel threshold and drain induced barrier lowering (DIBL) effects. However, when the peak N.sup.- doping level is increased high enough for acceptable on-resistance, the drain field increases, giving rise to unacceptably high substrate and gate currents.
The so-called GOLD (gate overlapped drain) transistor, described by K. Izawa et al, IEEE Transactions on Electron Devices, Vol. 35, pp. 2088-2093 (1988) overcomes the N.sup.- resistance problem by inducing a channel in the LDD regions with the overlapping gate. This comes at the expense of lower packing density and large Miller capacitance.
The short channel metal-oxide semiconductor devices are separated from neighboring devices by a trench whose sidewalls are lined with an oxide liner, such as by steam oxidation. The trench is then filled with an oxide filler, such as by TEOS (tetra-ethyl orthosilicate). Each device comprises (a) lightly doped source and drain regions having a first conductivity separated by a gate region, (b)) a shallow channel doping region having a second conductivity opposite to the first conductivity and formed in the gate region, (c) doped polysilicon contacts contacting each of the source and drain regions, (d) a gate oxide formed over the gate region, and (e) a gate electrode comprising polysilicon having the first conductivity, the gate electrode separated from the source and drain contacts by an oxide.
This basic trench configuration of short channel metal-oxide semiconductor devices enables industry to achieve reduced dimensions in MOS transistor technology. However, enthusiasm in the semiconductor industry for this configuration has been dampened by problems deriving from the formation of parasitic devices in the trench sidewalls as well as low drive currents. More specifically, in performing etching processes necessary to manufacture such MOS devices, it is possible to etch the TEOS layer into the trench, so that the trench sidewalls are exposed. As a result, this exposed Si surface forms part of the gate region and causes (1) degraded carrier mobility in the mechanically-stressed curved region with lower saturation current; and (2) an accumulation of dopant near the exposed surface which remits in spatial variations of threshold voltage.
Accordingly, there remains a need for improving drive currents, eliminating sidewall trench parasitics, and simplifying trench filling TEOS polishing in CMOS transistors having sub-micrometer channel lengths.